USING TIME ZONES FOR DATA-PATH ALLOCATION IN HIGH-LEVEL SYNTHESIS OF DIGITAL-SYSTEMS

The paper describes the data path allocation in high-level synthesis of digital systems using a new approach named the time-zone approach. Using the time-zone approach, where time steps are partitioned into zones, the register allocation and the module allocation for a given scheduled data flow graph (DFG) are performed in the same phase. The number of registers required to store the values in the DFG is minimized, and at the same time the interconnections between the registers and the modules (as well as the number of multiplexers required) are optimized. The experimental results obtained from testing several published benchmarks show that the allocation results are improved in terms of reduction of interconnections and the number of multiplexers and registers.