MULTIPLIER-FREE IIR FILTER REALIZATION USING PERIODICALLY TIME-VARYING STATE-SPACE STRUCTURE .2. VLSI ARCHITECTURES

被引：2
|
作者：
GHANEKAR, S
TANTARATANA, S
FRANKS, LE
机构：
[1] Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA
来源：
IEEE TRANSACTIONS ON SIGNAL PROCESSING | 1994年 / 42卷 / 05期
基金：
美国国家科学基金会;
关键词：
D O I：
10.1109/78.295215
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In Part I of this paper, a multiplier-free realization for IIR filters based on periodically time-varying state-space (PTV-SS) systems was proposed. Each biquad unit of the given target filter is realized with a higher order PTV-SS system operating at a higher speed. The coefficients of the PTV-SS system are restricted to a few power-of-two values. Therefore, such a structure can be implemented using shift and accumulate operations. In this paper, nonsystolic as well as systolic architectures for VLSI implementations of the PTV-SS system are developed. Different architectures are obtained using different timings and locations of the shift-and-accumulate operations. The design process is illustrated for a fourth-order PTV-SS system.
引用
收藏
页码：1018 / 1027
页数：10
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