MULTIPLIER-FREE IIR FILTER REALIZATION USING PERIODICALLY TIME-VARYING STATE-SPACE STRUCTURE .2. VLSI ARCHITECTURES

In Part I of this paper, a multiplier-free realization for IIR filters based on periodically time-varying state-space (PTV-SS) systems was proposed. Each biquad unit of the given target filter is realized with a higher order PTV-SS system operating at a higher speed. The coefficients of the PTV-SS system are restricted to a few power-of-two values. Therefore, such a structure can be implemented using shift and accumulate operations. In this paper, nonsystolic as well as systolic architectures for VLSI implementations of the PTV-SS system are developed. Different architectures are obtained using different timings and locations of the shift-and-accumulate operations. The design process is illustrated for a fourth-order PTV-SS system.