A LARGE-BIAS CONDUCTION MODEL OF POLYCRYSTALLINE SILICON FILMS

There exists a need for a large-bias conduction model of polysilicon films used in VLSI/ULSI and in high power integrated circuits. A large-bias conduction model has been developed by extending the emission-based models of Lu et al. [13] and Mandurah et al. [10] valid for small-bias, small-signal conditions. The following large-bias effects have been taken into account: 1) asymmetry of potential distribution around grain boundaries and 2) avalanche multiplication of carriers in the grain boundary layers at high electric fields. Since the exact nature of the grain boundary material is not yet known, and there is no direct method for determining the model parameters relating to grain boundaries, these were extracted by the parametric fitting of resistance versus temperature data of polysilicon resistors near room temperature with the above small-signal resistivity models modified by including Fermi-Dirac distribution. The model has been validated with experimental data on the current-voltage characteristics of ion-beam sputtered polysilicon resistors of different sizes and aspect ratios. The dependence of model parameters relating to grain boundary scattering and avalanche multiplication on the dimensions of resistors have been explained physically. The increased kink effect in polysilicon TFT's may also be predicted from the present theory. Some results on the I-V characteristics of polyresistors trimmed by high current pulses have been discussed qualitatively in the light of the present model. Although the model involves numerical integrations and a few iterations, it is reasonably fast in execution.