共 50 条
[43]
An optimal software-pipelining method for instruction-level parallel processors based on scaled retiming
[J].
ISPA 2001: PROCEEDINGS OF THE 2ND INTERNATIONAL SYMPOSIUM ON IMAGE AND SIGNAL PROCESSING AND ANALYSIS,
2001,
:405-410
[44]
Efficient instruction schedulers for SMT processors
[J].
TWELFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS,
2006,
:293-+
[45]
Reconfigurable instruction set processors: A survey
[J].
11TH IEEE INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS,
2000,
:168-173
[46]
Automatic Vector Instruction Selection for Dynamic Compilation
[J].
PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES,
2010,
:573-574
[47]
Instruction Scheduling for Reliability-Aware Compilation
[J].
2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC),
2012,
:1288-1296
[49]
Instruction mapping techniques for processors with very long instruction word architectures
[J].
JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS,
2022, 73 (06)
:387-395
[50]
Finding Speedup in Parallel Processors
[J].
PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON PARALLEL AND DISTRIBUTED COMPUTING,
2008,
:3-+