DESIGN AND VLSI IMPLEMENTATION OF A SYSTOLIC CORRELATOR

被引：0

作者：

DEZAN, C

GAUTRIN, E

QUINTON, P

机构：

[1] ENST,BRETAGNE,FRANCE

[2] INST RECH INFORMAT & SYST ALEATOIRES,F-35042 RENNES,FRANCE

来源：

ANNALES DES TELECOMMUNICATIONS-ANNALS OF TELECOMMUNICATIONS | 1991年 / 46卷 / 1-2期

关键词：

CORRELATOR; SYSTOLIC ARCHITECTURE; SIGNAL PROCESSING; PARALLEL PROCESSING; CIRCUIT DESIGN; INTEGRATED CIRCUIT; TESTABILITY; COMPUTER AIDED DESIGN;

D O I：

暂无

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

Many signal processing algorithms can be implemented on parallel architectures, whose regularity simplifies VLSI integration. In this paper, we present a systolic correlator, and we describe its VLSI implementation using full-custom, standard cell, and logical configurable arrays. We show how the architecture of this chip is formally derived using the Alpha language.

引用

页码：69 / 77

页数：9