Analysis and Design of high bit rate Clock-and-Data Recovery Circuits in CMOS Technology

被引：0

作者：

Bremer, J-K ^{[1
]}

Zemko, C. ^{[1
]}

Schmackers, J. ^{[1
]}

Mathis, W. ^{[1
]}

机构：

[1] Leibniz Univ Hannover, Inst Theoret Elektrotech, Appelstr 9A, D-30167 Hannover, Germany

来源：

ADVANCES IN RADIO SCIENCE | 2007年 / 5卷

关键词：

Flip flop circuits;

D O I：

10.5194/ars-5-215-2007

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a novel realization concept for Clock-and-Data-Recovery circuits. Our Design uses a nonlinear phase detector architecture, which is based on the Alexander phase detection method. In order to ensure circuit functionality in the RF region, we use very fast switching HLO-Flip-Flops (high-speed latching operation flip-flop) in our design. The primal goal in our design was the minimization of self induced jitter of the phase detector. The accuracy of our circuit design and the functionality in the GHz regime is confirmed by various circuit simulations executed with the SPECTRE Simulator.

引用

页码：215 / 219

页数：5

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