SIGNATURE ANALYSIS - SIMULATION OF INVENTORY, CYCLE TIME, AND THROUGHPUT TRADE-OFFS IN WAFER FABRICATION

被引：17
作者：
ATHERTON, RW
DAYHOFF, JE
机构：
[1] IN MOTION TECHNOL,LOS ALTOS,CA 94022
[2] JUDITH DAYHOFF & ASSOCIATES,MT VIEW,CA 94043
来源：
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1986年 / 9卷 / 04期
关键词：
D O I：
10.1109/TCHMT.1986.1136668
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
引用
收藏
页码：498 / 507
页数：10
相关论文
共 14 条
[1]  
ATHERTON RW, 1985, SEMICONDUCTOR WO AUG, P137
[2]  
ATHERTON RW, 1985, SEMICON W TECHNICAL, P63
[3]  
ATHERTON RW, 1985, ECS ABST, P146
[4]  
ATHERTON RW, 1983, 1984 P INT TEST C, P418
[5]  
Buffa E. S., 1979, PRODUCTION INVENTORY
[6]  
Cooper Robert B., 1981, INTRO QUEUEING THEOR
[7]   SIGNATURE ANALYSIS OF DISPATCH SCHEMES IN WAFER FABRICATION [J].
DAYHOFF, JE ;
ATHERTON, RW .
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1986, 9 (04) :518-525
[8]  
DAYHOFF JE, 1985, ECS ABST, P144
[9]  
DAYHOFF JE, 1984, VLSI DESIGN DEC, P84
[10]  
Frauchiger D., 2013, PRINCIPLES DISCRETE
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