A VLSI ARCHITECTURE FOR THE ALTERNATIVE SUBSAMPLING-BASED BLOCK MATCHING ALGORITHM

被引：9

作者：

JUNG, HK ^{[1
]}

HONG, CP ^{[1
]}

CHOI, JS ^{[1
]}

HA, YH ^{[1
]}

机构：

[1] TAEGU UNIV,DEPT COMP SCI,KYUNGPOOK 713714,SOUTH KOREA

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1995年 / 41卷 / 02期

关键词：

D O I：

10.1109/30.391351

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A VLSI architecture of the block matching algorithm based on the alternative subsampling method for motion estimation is proposed. The alternative subsampling method reduces the computational complexity by alternatively subsampling the number of pixels within the blocks used to estimate motion vectors, whereas conventional methods limit the number of locations searched. Simulation results show that the performance of this method is very close to full search algorithm For subsampling factor of N, this approach can achieve approximately N/2 times of calculation with additional small overhead associated with address generator and temporary buffer. In addition, this architecture has about a half silicon area compared to Yang's architecture.

引用

页码：239 / 247

页数：9

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