TRANSIENT MODEL FOR GATE TURN-OFF THYRISTOR IN POWER ELECTRONIC SIMULATIONS

A two-level device model for a gate turn-off thyristor (GTO) is presented to predict its transient behaviour especially for turn-off. The model is developed mainly on the basis of the semiconduction phenomenon and is represented in a subcircuit form for easy adaption to currently used circuit simulators. The level 1 model is formed by switching network paralleled with a recovery circuit and is able to simulate the GTO switching with short simulation time but acceptable accuracy. The level 2 model incorporated the Hu-KI SCR model and additional charge control, anode-cathode and gate-cathode resistance modulation networks to simulate turn-off phenomena more precisely. The validity of the model is verified by comparing with experimental results. Methods for determination of the model parameters are described.