Josephson Junction Integrated Circuit Process with Planarized PECVD SiO2 Dielectric

被引：4

作者：

Barfknecht, A. T. ^{[1
]}

Ruby, R. C. ^{[2
]}

Ko, H. L. ^{[2
]}

Lee, G. S. ^{[2
]}

机构：

[1] Conductus Inc, 969 W Maude Ave, Sunnyvale, CA 94086 USA

[2] Hewlett Packard Labs, 3500 Deer Creek Rd, Palo Alto, CA 94303 USA

来源：

IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 1993年 / 3卷 / 01期

关键词：

D O I：

10.1109/77.233940

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As part of our efforts to reach very-large-scale integration for our Nb Josephson junction circuits, we have developed a process technology that includes plasma enhanced chemical vapor deposited SiO2 for all interlayer dielectrics, as well as sacrificial resist etch-back planarization to smooth the surface topology under the trilayer.

引用

页码：2201 / 2203

页数：3

共 12 条

[1]

ADAMS AC, 1981, SOLID STATE TECHNOL, V24, P178

[2] A SIMPLE AND ROBUST NIOBIUM JOSEPHSON JUNCTION INTEGRATED-CIRCUIT PROCESS [J].

BARFKNECHT, AT ;

RUBY, RC ;

KO, H .

IEEE TRANSACTIONS ON MAGNETICS, 1991, 27 (02) :3125-3128

[3]

Gronberg L., 1992, Superconducting Devices and their Applications. Proceedings of the 4th International Conference SQUID '91 (Sessions on Superconducting Devices), P281

[4]

Hayakawa H, COMMUNICATION

[5] APPLICATION OF SPUTTERED SIO2 INSULATOR TO NB/ALOX/NB JOSEPHSON-JUNCTIONS [J].

HOKO, H ;

IMAMURA, T ;

OHARA, S ;

HASUO, S .

JOURNAL OF APPLIED PHYSICS, 1987, 62 (08) :3432-3435

[6] A SUBMICROMETER NB/ALOX/NB JOSEPHSON JUNCTION [J].

IMAMURA, T ;

HASUO, S .

JOURNAL OF APPLIED PHYSICS, 1988, 64 (03) :1586-1588

[7] SUB-MU-M, PLANARIZED, NB-ALOX-NB JOSEPHSON PROCESS FOR 125-MM WAFERS DEVELOPED IN PARTNERSHIP WITH SI TECHNOLOGY [J].

KETCHEN, MB ;

PEARSON, D ;

KLEINSASSER, AW ;

HU, CK ;

SMYTH, M ;

LOGAN, J ;

STAWIASZ, K ;

BARAN, E ;

JASO, M ;

ROSS, T ;

PETRILLO, K ;

MANNY, M ;

BASAVAIAH, S ;

BRODSKY, S ;

KAPLAN, SB ;

GALLAGHER, WJ ;

BHUSHAN, M .

APPLIED PHYSICS LETTERS, 1991, 59 (20) :2609-2611

[8] SUB-MU-M LINEWIDTH INPUT COILS FOR LOW T(C) INTEGRATED THIN-FILM DC SUPERCONDUCTING QUANTUM INTERFERENCE DEVICES [J].

KETCHEN, MB ;

STAWIASZ, KG ;

PEARSON, DJ ;

BRUNNER, TA ;

HU, CK ;

JASO, MA ;

MANNY, MP ;

PARSONS, AA ;

STEIN, KJ .

APPLIED PHYSICS LETTERS, 1992, 61 (03) :336-338

[9] PLANARIZATION TECHNOLOGY FOR JOSEPHSON INTEGRATED-CIRCUITS [J].

NAGASAWA, S ;

TSUGE, H ;

WADA, Y .

IEEE ELECTRON DEVICE LETTERS, 1988, 9 (08) :414-416

[10] APPLICATION OF A 2-LAYER PLANARIZATION PROCESS TO VLSI INTERMETAL DIELECTRIC AND TRENCH ISOLATION PROCESSES [J].

SHELDON, DJ ;

GRUENSCHLAEGER, CW ;

KAMMERDINER, L ;

HENIS, NB ;

KELLEHER, P ;

HAYDEN, JD .

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1988, 1 (04) :140-146

← 1 2 →