DESIGN OF SWITCHED-CAPACITOR FIR FILTERS WITH APPLICATION TO A LOW-POWER MFSK RECEIVER

被引:5
作者
DABROWSKI, A
MENZI, U
MOSCHYTZ, GS
机构
[1] Swiss Federal Inst of Technology, Zurich
来源
IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS | 1992年 / 139卷 / 04期
关键词
FINITE IMPULSE RESPONSE (FIR) FILTERS; SWITCHED-CAPACITOR (SC) FILTERS; MINIMUM FREQUENCY SHIFT KEYING (MFSK) MODULATION;
D O I
10.1049/ip-g-2.1992.0072
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Finite impulse response (FIR) switched-capacitor (SC) filters for minimum frequency-shift keying (MFSK) demodulation techniques have been developed and are discussed. The proposed filters comprise combinations of the following building blocks: sample-and-hold circuits, even-odd delay circuits, Gillingham delay circuits, recharge memory elements, Lee-Martin summer circuits, recharge summer circuits, and rotator switches. These are described in the paper. Furthermore, composite SC filter structures are derived using a morphological approach. The FIR SC filter structures are compared and evaluated with respect to the required chip area when implemented in 3-mu-m CMOS technology, and, by computer simulation, with regard to bit error probability when used in an MFSK receiver. It is shown that the receiver performance is independent of the FIR filter structure used. Furthermore, using the FIR filters, and for a given bit error probability, the required signal-to-noise ratio (SNR) is actually 3 dB lower than for a typical commercial MFSK receiver (e.g. an MB87002).
引用
收藏
页码:450 / 466
页数:17
相关论文
共 20 条
[1]  
Allen P.E., 1984, SWITCHED CAPACITOR C
[2]   OFFSET-COMPENSATED SWITCHED-CAPACITOR DELAY-CIRCUIT THAT IS INSENSITIVE TO STRAY CAPACITANCE AND TO CAPACITOR MISMATCH [J].
DABROWSKI, A ;
MENZI, U ;
MOSCHYTZ, GS .
ELECTRONICS LETTERS, 1989, 25 (10) :623-625
[3]   PARASITIC-COMPENSATED SWITCHED-CAPACITOR DELAY-LINES [J].
DIAS, VF ;
FRANCA, JE .
ELECTRONICS LETTERS, 1988, 24 (07) :377-379
[4]   INTEGRATED TAPPED MOS ANALOG DELAY-LINE USING SWITCHED CAPACITOR TECHNIQUE [J].
ENOMOTO, T ;
ISHIHARA, T ;
YASUMOTO, MA .
ELECTRONICS LETTERS, 1982, 18 (05) :193-194
[5]   STRAY-FREE SWITCHED-CAPACITOR UNIT-DELAY CIRCUIT [J].
GILLINGHAM, P .
ELECTRONICS LETTERS, 1984, 20 (07) :308-310
[6]  
Gregorian R., 1986, ANALOG MOS INTEGRATE, P505
[7]  
GUBSER A, 1988, MINIMUM FREQUENCY SH
[8]  
GUBSER A, 1989, THESIS SWISS FEDERAL
[9]   A SWITCHED-CAPACITOR REALIZATION OF MULTIPLE FIR FILTERS ON A SINGLE CHIP [J].
LEE, YS ;
MARTIN, KW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (02) :536-542
[10]  
MENZI U, AGEN MITTEILUNGEN, V49, P37