A 1.9 mu W Transient-Enhanced Low-Dropout Regulator with Voltage-Spike Suppression

A low-voltage low-dropout regulator (LDO) with voltage-spike suppression is presented in this paper. The proposed LDO is formed by multiple gain stages to improve the loop gain and loop bandwidth simultaneously. The LDO is compensated by a zero generated by the equivalent series resistance (ESR) of the output capacitor, as well as a zero created by the high-pass feedback network. Moreover, the structure contains a capacitive-coupling push-pull stage controlled by a voltage comparator to improve slew rate at the gate of the power transistor in order to suppress the output voltage spike without increasing the bias current. The proposed LDO is implemented by a 0.35-mu m CMOS technology (V-THN approximate to 0 . 5 V and V-THP approximate to-0 . 65 V). The active area of the chip is 310 mu mx1010 mu m. The minimum operating input voltage is 1 V and the preset output voltage is 0.9 V, with quiescent current of 1.9 mu A. Measured maximum output current is 91 mA. Load transient measurement shows the voltage spike can be completely suppressed.