EVALUATING DESIGN CHOICES FOR SHARED BUS MULTIPROCESSORS IN A THROUGHPUT-ORIENTED ENVIRONMENT

This paper considers the evaluation of design choices in multiprocessors with a single, shared bus interconnect operating in a throughput-oriented, multiprogrammed environment, that is, an environment in which each task is being executed on a single processor and the performance of the multiprocessor is measured by its overall throughput. To evaluate design choices, we develop mean value analysis analytical models and validate our models by comparing their results against the results of a trace-driven simulation analysis for 5376 multiprocessor configurations. The trace-driven simulation uses actual programs and simulates their execution in a throughput-oriented environment. Using multiprocessor throughput as a performance metric and the mean value analysis models as tools, we evaluate several design choices. We find that: 1) cache block sizes that yield the best performance in a multiprocessor differ from the block sizes that yield the best uniprocessor performance metrics, 2) a larger cache set associativity might be warranted in a multiprocessor even though it might not be warranted in a uniprocessor, 3) a split transaction, pipelined bus yields much higher multiprocessor throughput than a circuit switched bus, especially for larger main memory latencies, and 4) increasing the bus width appears to be an effective way of improving multiprocessor throughput.