A FAULT TOLERANT MASSIVELY PARALLEL PROCESSING ARCHITECTURE

被引:14
|
作者
BALASUBRAMANIAN, V
BANERJEE, P
机构
关键词
D O I
10.1016/0743-7315(87)90025-6
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
引用
收藏
页码:363 / 383
页数:21
相关论文
共 50 条
  • [21] Optimizing ultra high-resolution video processing on mobile architecture with massively parallel processing
    Shin W.
    Baek N.
    IEIE Transactions on Smart Processing and Computing, 2021, 10 (02): : 84 - 89
  • [22] A novel architecture for a massively parallel low level vision processing engine on chip
    Tomasi, Matteo
    Vanegas, Mauricio
    Barranco, Francisco
    Diaz, Javier
    Ros, Eduardo
    IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE 2010), 2010, : 3033 - 3039
  • [23] Massively Parallel Big Data Classification on a Programmable Processing In-Memory Architecture
    Kim, Yeseong
    Imani, Mohsen
    Gupta, Saransh
    Zhou, Minxuan
    Rosing, Tajana S.
    2021 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN (ICCAD), 2021,
  • [24] A massively parallel EZW processing architecture for real-time video coding
    Alagoda, G
    Rassau, A
    Eshraghian, K
    6TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL XIV, PROCEEDINGS: IMAGE, ACOUSTIC, SPEECH AND SIGNAL PROCESSING III, 2002, : 304 - 309
  • [25] A fault-tolerant architecture for parallel applications in tiled-CMPs
    Sanchez, Daniel
    Aragon, Juan L.
    Garcia, Jose M.
    JOURNAL OF SUPERCOMPUTING, 2012, 61 (03): : 997 - 1023
  • [26] A fault-tolerant architecture for parallel applications in tiled-CMPs
    Daniel Sánchez
    Juan L. Aragón
    José M. García
    The Journal of Supercomputing, 2012, 61 : 997 - 1023
  • [27] The flexible hypercube: A new fault-tolerant architecture for parallel computing
    Hameenanttila, T
    Guan, XL
    Carothers, JD
    Chen, JX
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1996, 37 (02) : 213 - 220
  • [29] Design of fault-tolerant ATM switch based on parallel architecture
    Segkhoonthod, S
    Sinclair, MC
    ELECTRONICS LETTERS, 1997, 33 (15) : 1289 - 1290
  • [30] ARCHITECTURE FOR A MASSIVELY PARALLEL DATABASE MACHINE
    RISHE, N
    TAL, D
    LI, Q
    MICROPROCESSING AND MICROPROGRAMMING, 1989, 25 (1-5): : 33 - 38