BUILT-IN SELF-TEST OF DIGITAL DECIMATORS

被引:1
作者
ADHAM, S
KASSAB, M
RAJSKI, J
TYSZER, J
机构
[1] MCGILL UNIV,DEPT ELECT ENGN,MICROELECTR & COMP SYST LAB,MONTREAL,PQ H3A 2A7,CANADA
[2] MENTOR GRAPH CORP,WILSONVILLE,OR 97070
来源
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1995年 / 42卷 / 07期
关键词
D O I
10.1109/82.401174
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief demonstrates a new built-in self test (BIST) scheme designated to improve a testability of digital decimators - commonly used building blocks in digital signal processing (DSP) environment. The proposed solution takes the advantage of operations offered by already existing functional blocks to perform basic testing functions. Thus it drastically reduces the need for an additional testing hardware as well as it eliminates the performance degradation usually introduced by traditional BIST schemes. An easy to test implementation of the decimator based on a custom data-path architecture is also analyzed.
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页码:486 / 492
页数:7
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