DIGITAL NEURON MODEL USING DIGITAL PHASE-LOCKED LOOP

被引:0
|
作者
TOKUNAGA, M
SASASE, I
MORI, S
机构
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We propose a new type of the digital neuron model by using multi-input multilevel-quantized digital phase-locked loop (MM-DPLL), where the input is represented by the phase modulated signal. It is shown that this model has the characteristics of the neuron; spatial summation, temporal summation and thresholding. We applied our model to the pattern recognition and to the Hopefield type associative memory, in order to verify that the network by this model can operate properly. In the pattern recognition, we used the perceptron convergence procedure (delta rule), and confirm the possibility of learning by modifying the connection weights. In the associative memory, we confirm that the network can learn five digit patterns of the fundamental memories, and also can recall the correct pattern for the noisy input pattern.
引用
收藏
页码:615 / 621
页数:7
相关论文
共 50 条
  • [1] Markov model for digital phase-locked loop
    Samokhvalov, A.A.
    Kondrat'ev, A.V.
    Timofeev, A.A.
    Elektromagnitnye Volny i Elektronnye Systemy, 2005, 10 (06): : 47 - 55
  • [2] DIGITAL PHASE-LOCKED LOOP.
    Furtney Jr., R.W.
    1884, (17):
  • [3] DYNAMICS OF DIGITAL PHASE-LOCKED LOOP
    MAKSAKOV, VP
    RADIOTEKHNIKA I ELEKTRONIKA, 1988, 33 (05): : 999 - 1007
  • [4] DIGITAL PHASE-LOCKED LOOP MODELS
    BELYKH, VN
    RADIOTEKHNIKA I ELEKTRONIKA, 1979, 24 (11): : 2244 - 2253
  • [5] JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP
    YAMASHITA, M
    TSUJI, T
    NISHIMURA, T
    MURATA, M
    NAMEKAWA, T
    PROCEEDINGS OF THE IEEE, 1976, 64 (11) : 1640 - 1641
  • [6] A digital phase-locked loop for frequency detection
    Werter, JM
    38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1996, : 1252 - 1255
  • [7] A design method for digital phase-locked loop
    Ru Jiyuan
    Liu Yujia
    Xue Wei
    PROCEEDINGS OF THE 2015 4TH NATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER ENGINEERING ( NCEECE 2015), 2016, 47 : 1471 - 1475
  • [8] Implementation of a digital phase-locked loop using CORDIC algorithm
    Vuori, J
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 164 - 167
  • [9] GRAPHICAL ANALYSIS OF A DIGITAL PHASE-LOCKED LOOP
    RUSSO, F
    IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 1979, 15 (01) : 88 - 94
  • [10] DIGITAL PHASE-LOCKED LOOP WITH JITTER BOUNDED
    WALTERS, SM
    TROUDET, T
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (07): : 980 - 987