A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

被引:7
作者
Li, Gang [1 ]
Wang, Pengjun [1 ,2 ]
Kang, Yaopeng [1 ]
Zhang, Yuejun [1 ]
机构
[1] Ningbo Univ, Fac Elect Engn & Comp Sci, Ningbo 315211, Zhejiang, Peoples R China
[2] Wenzhou Univ, Coll Math Phys & Elect Informat Engn, Wenzhou 325035, Peoples R China
基金
中国国家自然科学基金;
关键词
CNFETs; ternary SRAM cell; low standby-power; high stability;
D O I
10.1088/1674-4926/39/8/085002
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors (CNFETs). The performance is simulated in terms of three criteria including standby-power, delay (write and read) and stability (RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01x and 1.95x of the conventional and novel ternary SRAM cells, respectively.
引用
收藏
页数:7
相关论文
共 14 条
[1]   A novel design of low power and high read stability Ternary SRAM (T-SRAM), memory based on the modified Gate Diffusion Input (m-GDI) method in nanotechnology [J].
Abiri, Ebrahim ;
Darabi, Abdolreza .
MICROELECTRONICS JOURNAL, 2016, 58 :44-59
[2]   Carbon nanotubes for high-performance electronics - Progress and prospect [J].
Appenzeller, J. .
PROCEEDINGS OF THE IEEE, 2008, 96 (02) :201-211
[3]  
Cho G, 2011, INTEGR VLSI J, V54, P97
[4]   A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application - Part I: Model of the intrinsic channel region [J].
Deng, Jie ;
Wong, H. -S. Philip .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (12) :3186-3194
[5]  
Ghanatghestani M. Mohammadi, 2015, J COMPUT THEOR NANOS, V12, P1, DOI DOI 10.1166/JCTN.2015.4546
[6]   Noise Margin-Optimized Ternary CMOS SRAM Delay and Sizing Characteristics [J].
Kamar, Zafrullah ;
Nepal, Kundan .
53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, :801-804
[7]   Design of a Ternary Memory Cell Using CNTFETs [J].
Lin, Sheng ;
Kim, Yong-Bin ;
Lombardi, Fabrizio .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2012, 11 (05) :1019-1025
[8]   High-performance carbon nanotube field-effect transistor with tunable Polarities [J].
Lin, YM ;
Appenzeller, J ;
Knoch, J ;
Avouris, P .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2005, 4 (05) :481-489
[9]   Low-power fast (LPF) SRAM cell for write/read operation [J].
Prabhu, C. M. R. ;
Singh, Ajay Kumar .
IEICE ELECTRONICS EXPRESS, 2011, 8 (18) :1473-1478
[10]   Scaling carbon nanotube complementary transistors to 5-nm gate lengths [J].
Qiu, Chenguang ;
Zhang, Zhiyong ;
Xiao, Mengmeng ;
Yang, Yingjun ;
Zhong, Donglai ;
Peng, Lian-Mao .
SCIENCE, 2017, 355 (6322) :271-+