AN EXTENSION OF PROBABILISTIC SIMULATION FOR RELIABILITY-ANALYSIS OF CMOS VLSI CIRCUITS

The probabilistic simulation approach [1] is extended to include the computation of the variance waveform of the power/ground current, in addition to its expected waveform. To provide the motivation for doing this, we focus on the problem of estimating the median time-to-failure (MTF) due to electromigration (EM) in the power and ground buses of CMOS circuits. New theoretical results are presented that quantify the relationship between the MTF and the statistics of the stochastic current. This leads to a more accurate estimate of the MTF that requires both the expected and variance waveforms. A novel technique is then presented to compute the variance waveform for CMOS circuits, which has been incorporated into the probabilistic simulator CREST [1]. We show results of this implementation, demonstrating efficiency and accuracy on a number of circuits. We also use these results to study the importance of the variance waveform by estimating its contribution to the MTF relative to that of the expected waveform.