AUTOMATED SYNTHESIS OF ASYNCHRONOUS INTERFACE CIRCUITS

被引:0
作者
LAVAGNO, L
SANGIOVANNIVINCENTELLI, A
机构
[1] Department of EECS, University of California, Berkeley
关键词
ASYNCHRONOUS INTERFACE CIRCUITS; SIGNAL TRANSITION GRAPHS; VMEBUS;
D O I
10.1016/0141-9331(93)90021-X
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes a design methodology for asynchronous interface circuits through an example, a VMEbus master interface. The circuit and the environment where it operates are described using a formalization of timing diagrams, the signal transition graph. A standard cell implementation of the circuit is automatically derived from the specification. Then the implementation is automatically analysed for potential hazards, and information on the internal gate delays and external environment delays is used to verify that the circuit is hazard-free. If such hazard verification fails (e.g. due to tolerances in the delay information), then delay buffers are automatically inserted, producing a hazard-free, albeit slower, circuit.
引用
收藏
页码:232 / 242
页数:11
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