STATIC CMOS LATCH-UP CONSIDERATIONS IN HVIC DESIGN

被引：7

作者：

HUANG, Q

AMARATUNGA, GAJ

NARAYANAN, EMS

MILNE, WI

机构：

[1] Department of Engineering, University of Cambridge, Cambridge

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 02期

关键词：

Computer Simulation - Semiconductor Devices; MOS;

D O I：

10.1109/4.52192

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Static latch-up in CMOS devices placed on a thin epitaxial layer for high-voltage integrated circuits (HVIC’s) is investigated using SPICE. The layout configuration and the high-voltage device substrate current have a major influence on CMOS latch-up when compared with conventional CMOS structures. Special latch-up conditions exist for NMOS adjacent to high-voltage devices due to an extra p-n-p-n path. The results suggest that PMOS adjacent to the high-voltage device is best suited, in terms of layout, to avoiding latch-up conditions. It is also shown that the latch-up of CMOS devices is improved by placing them in an n- epitaxial layer on a p- substrate. 0018-9200/90/0400-0613$01.00 © 1990 IEEE

引用

页码：613 / 616

页数：4

共 4 条

[1]

APPELS JA, 1979, IEDM, P238

[2] COMPUTATION OF STEADY-STATE CMOS LATCHUP CHARACTERISTICS [J].