FAULT-TOLERANCE CONSIDERATIONS FOR REDUNDANT BINARY-TREE-DYNAMIC RANDOM-ACCESS-MEMORY (RAM) CHIPS

被引:1
作者
CICIANI, B
机构
[1] University of Rome, Rome
关键词
FAULT-TOLERANT MEMORY; MEMORY PERFORMABILITY; MEMORY YIELD; YIELD EVALUATION; VLSI CHIP DESIGN; VLSI MEMORY;
D O I
10.1109/24.126688
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The binary-tree-dynamic RAM (TRAM) (Patent application #60882 on the TRAM architecture is pending with the US Patent Office) architecture has been proposed to overcome the performance and testing time limits of the traditional architecture of memory chips. A 64 Mb prototype of this architecture is being built by a DRAM manufacturer in Japan. This paper investigates manufacturing yield and operational performance of redundant TRAMs with respect to variation of tree depth and redundancy level. For this purpose, a based chip area, a yield and operational performance FoM (figure of merit) allowing the comparison of various choices has been formulated and used. The yield is evaluated by a new Markov-chain based model. The memory operational performance has been analyzed by an innovative technique that substitutes the notion of chip state at the end of the mission time with the cumulative work performed by the chip during the mission time (performability). The FoM is - very straightforward and extremely easy to use in parametric studies of chip yield and operational performance vs redundancy level and reconfiguration strategy quite versatile for inclusion in CAM/CAD programming environments is appropriate for both VLSI chip designers and users in choosing the most suitable architecture. An optimum value of the tree depth and redundancy level were found for a given RAM size, the adopted reconfiguration strategy, and the kind of redundancies. This is the result of a tradeoff between yield and operational performance. Indeed, independently of the number of spot manufacturing faults in the memory leaf, it is possible to find a redundancy level that can tolerate it; then the lesser the tree-depth, the greater the average wafer area needed to produce an acceptable chip. But, on the other hand, the bigger the tree-depth, the better the operational performance. To evaluate the FoM, some assumptions, derived from the literature and experience, were adopted. While some of these assumptions can be changed, the methodology remains the same.
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页码:139 / 148
页数:10
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