ATM SWITCH ARCHITECTURES WITH INPUT OUTPUT-BUFFERING - EFFECT OF INPUT TRAFFIC CORRELATION, CONTENTION RESOLUTION POLICIES, BUFFER ALLOCATION STRATEGIES AND DELAY IN BACKPRESSURE SIGNAL

This paper investigates the robustness of nonblocking ATM switch architectures with input-output-buffering and backpressure control under correlated input traffic conditions. Traffic correlation is modeled by two parameters: the mean active duration of the ON-OFF source feeding each input port and the spacing between the cells generated within an active period. This spacing can be fixed or random. The effect of these parameters on the switch performance in terms of the maximum switch throughput, and the cell loss behavior is investigated. The gain in throughput provided by the input-output-buffered architecture and the backpressure control mechanism over the pure input buffered architecture is investigated for different switch sizes and mean burst lengths. Detailed algorithmic descriptions and a possible implementation approach of the different selection mechanisms needed to resolve output port contention are presented. The performance of these selection mechanisms is evaluated, taking into consideration the performance enhancements provided by incorporating different arbitration criteria within the selection mechanisms. The critical issue of allocating the available buffer memory between the input and output ports for a fixed buffer budget is examined. The effect of traffic correlation on the buffer allocation strategies is also presented. The problems caused by the delay in the backpressure signal arising in possible implementations, particularly in a centralized control approach, are presented and analyzed in detail.