HARDWARE APPROACHES TO CACHE COHERENCE IN SHARED-MEMORY MULTIPROCESSORS .2.

被引：10
|
作者：
TOMASEVIC, M [1 ]
MILUTINOVIC, V [1 ]
机构：
[1] MICHAEL PUPIN INST, BELGRADE, YUGOSLAVIA
来源：
IEEE MICRO | 1994年 / 14卷 / 06期
关键词：
D O I：
10.1109/40.331392
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Improving performance and scalability in shared-memory multiprocessors requires an appropriate solution to the well-known cache coherence problem. Hardware schemes-highly convenient because of their transparency for software-offer fully dynamic solutions, with an ability to achieve high performance. In Part 1 of this two-part series, we discussed the principles of the two major groups of hardware protocols and summarized relevant representatives. Here, we also briefly consider the coherence problem in multilevel cache hierarchies and large-scale, shared-memory multiprocessors.
引用
收藏
页码：61 / 66
页数：6
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