HW-SW CO-DESIGN OF MPSOC USING FGPA IP CORES

被引:0
作者
Nita, Iulian [1 ]
Zdru, Gabriel [1 ]
机构
[1] Univ Politehn Bucuresti, Dept Appl Elect & Informat Technol, Bucharest, Romania
来源
UNIVERSITY POLITEHNICA OF BUCHAREST SCIENTIFIC BULLETIN SERIES C-ELECTRICAL ENGINEERING AND COMPUTER SCIENCE | 2013年 / 75卷 / 01期
关键词
Multiprocessor System on Chip; FPGA; MicroBlaze; image filtering;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The new design technologies of multiprocessor systems on chip based on FPGAs and IP blocks, make possible the development of optimized devices in terms of performance, power consumption and cost. Flexibility offered by these new design tools allow design space exploration to search for the most effective implementations. Thus, in this paper, we performed a research on these technologies and we have proposed a hardware / software co-design model for developing applications on multiprocessor systems on chip based on FPGA IP cores. The experimental results were validated with an application for filtering images, implemented on a multiprocessor system using the development kit Xilinx XUP Virtex 5 and Xilinx EDK application software
引用
收藏
页码:135 / 150
页数:16
相关论文
共 38 条
  • [21] Toward Efficient Co-Design of CNN Quantization and HW Architecture on FPGA Hybrid-Accelerator
    Zhang, Yiran
    Li, Guiying
    Yuan, Bo
    2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024, 2024, : 678 - 683
  • [22] Open-Source HW/SW Co-Simulation Using QEMU and GHDL for VHDL-Based SoC Design
    Biagetti, Giorgio
    Falaschetti, Laura
    Crippa, Paolo
    Alessandrini, Michele
    Turchetti, Claudio
    ELECTRONICS, 2023, 12 (18)
  • [23] Co-design of a TinyLLM using Programmable Logic and Software on an FPGA
    Muller, Michael
    Tyshka, Alexander
    Theisen, Max
    Hanna, Darrin
    2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024, 2024, : 253 - 257
  • [24] Area and Power Analysis of AES using Hardware and Software Co-Design
    Deotare, Vilas V.
    Padole, Dinesh V.
    Wakode, Ashok S.
    2014 IEEE GLOBAL CONFERENCE ON WIRELESS COMPUTING AND NETWORKING (GCWCN), 2014, : 194 - 198
  • [25] Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms
    Colangelo, Philip
    Segal, Oren
    Speicher, Alex
    Margala, Martin
    2019 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2019,
  • [26] A Hardware/Software Co-Design System using reconfigurable computing technology
    Casselman, S
    Schewel, J
    INTELLIGENT SYSTEMS IN DESIGN AND MANUFACTURING, 1998, 3517 : 208 - 214
  • [27] FPGA Implementation of Blokus Duo Player using Hardware/Software Co-Design
    Kojima, Akira
    PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), 2014, : 378 - 381
  • [28] Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs
    Han, Yan
    Virupakshappa, Kushal
    Pinto, Esdras Vitor Silva
    Oruklu, Erdal
    ELECTRONICS, 2015, 4 (04) : 1062 - 1089
  • [29] Acceleration of Fractal Image Compression Using the Hardware-Software Co-Design Methodology
    Alvarado Nava, Oscar
    Diaz Perez, Arturo
    2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS, 2009, : 167 - +
  • [30] Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm
    Migliore, Vincent
    Real, Maria Mendez
    Lapotre, Vianney
    Tisserand, Arnaud
    Fontaine, Caroline
    Gogniat, Guy
    IEEE TRANSACTIONS ON COMPUTERS, 2018, 67 (03) : 335 - 347