A detection for patent infringement suit via nanotopology induced by graph

被引：3

作者：

Thivagar, M. Lellis ^{[1
]}

Manuel, Paul ^{[2
]}

Devi, V. Sutha ^{[1
]}

机构：

[1] Madurai Kamaraj Univ, Sch Math, Madurai 625021, Tamil Nadu, India

[2] Kuwait Univ, Coll Comp Sci & Engn, Dept Informat Sci, Kuwait, Kuwait

来源：

COGENT MATHEMATICS | 2016年 / 3卷

关键词：

graph; neighbourhood; isomorphism; homeomorphism; electrical circuits;

D O I：

10.1080/23311835.2016.1161129

中图分类号：

O1 [数学];

学科分类号：

0701 ; 070101 ;

摘要：

The aim of this paper was to generate nanotopological structure on the power set of vertices of simple digraphs using new definition neighbourhood of vertices on out linked of digraphs. Based on the neighbourhood we define the approximations of the subgraphs of a graph. A new nanotopological graph reduction to symbolic circuit analysis is developed in this paper. By means of structural equivalence on nanotopology induced by graph we have framed an algorithm for detecting patent infringement suit.

引用

页数：10