AREA-TIME EFFICIENT MODULO 2(N)-1 ADDER DESIGN

被引：45
作者：
EFSTATHIOU, C [1 ]
NIKOLOS, D [1 ]
KALAMATIANOS, J [1 ]
机构：
[1] UNIV PATRAS,DEPT COMP ENGN,GR-26500 RIO PATRAS,GREECE
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1994年 / 41卷 / 07期
关键词：
CARRY LOOK-AHEAD ADDERS; MODULO 2(N)-1 ADDERS; END-AROUND CARRY ADDERS; VLSI ADDERS;
D O I：
10.1109/82.298378
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper the design of modulo 2n - 1 adders is discussed. Two new design procedures are given, based on the one-level and the two-level carry look-ahead addition algorithms. The adders designed according to the procedures proposed in this paper are significantly more efficient, with respect to speed and the cost function area-time product, than the corresponding adders already known from open literature.
引用
收藏
页码：463 / 467
页数：5
相关论文
共 22 条
[1]   NOVEL IMPLEMENTATION METHOD FOR ADDITION AND SUBTRACTION IN RESIDUE NUMBER-SYSTEMS [J].
BANERJI, DK .
IEEE TRANSACTIONS ON COMPUTERS, 1974, C 23 (01) :106-109
[2]   A VLSI IMPLEMENTATION OF RESIDUE ADDERS [J].
BAYOUMI, MA ;
JULLIEN, GA ;
MILLER, WC .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1987, 34 (03) :284-288
[3]   A LOOK-UP TABLE VLSI DESIGN METHODOLOGY FOR RNS STRUCTURES USED IN DSP APPLICATIONS [J].
BAYOUMI, MA ;
JULLIEN, GA ;
MILLER, WC .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1987, 34 (06) :604-616
[4]  
ELLIETHY KM, 1992, IEEE T CIRC SYST 2, V39, P226
[5]  
Garner H. L., 1959, IRE T ELECTRON COMPU, V8, P140, DOI DOI 10.1109/TEC.1959.5219515
[6]  
HUANG CH, 1981, IEEE T CIRCUITS SYST, V28, P32, DOI 10.1109/TCS.1981.1084905
[7]  
HWANG K, 1979, COMPUTER ARITHMETIC
[8]  
JENKINS WK, 1983, IEEE T COMPUT, V32, P388, DOI 10.1109/TC.1983.1676240
[9]  
JENKINS WK, 1977, IEEE T CIRCUITS SYST, V24, P191, DOI 10.1109/TCS.1977.1084321
[10]  
JULLIEN GA, 1978, IEEE T COMPUT, V27, P325, DOI 10.1109/TC.1978.1675105
123