AN EXPERIMENTAL 1-MBIT BICMOS DRAM

被引：12

作者：

KITSUKAWA, G ^{[1
]}

HORI, R ^{[1
]}

KAWAJIRI, Y ^{[1
]}

WATANABE, T ^{[1
]}

KAWAHARA, T ^{[1
]}

ITOH, K ^{[1
]}

KOBAYASHI, Y ^{[1
]}

OOHAYASHI, M ^{[1
]}

ASAYAMA, K ^{[1
]}

IKEDA, T ^{[1
]}

KAWAMOTO, H ^{[1
]}

机构：

[1] HITACHI LTD,CTR DEVICE DEV,OUME,TOKYO 198,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 05期

关键词：

DATA STORAGE; SEMICONDUCTOR - SEMICONDUCTOR DEVICES; BIPOLAR - SEMICONDUCTOR DEVICES; MOS;

D O I：

10.1109/JSSC.1987.1052796

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a P** plus buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1. 3- mu m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5. 0 multiplied by 14. 9 mm**2.

引用

页码：657 / 662

页数：6

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