DISTRIBUTING GATE-LEVEL DIGITAL TIMING SIMULATION OVER ARRAYS OF TRANSPUTERS

Continuing advances in VLSI fabrication technology are allowing circuit designs to become more and more complex and are thereby fuelling the need for ever-faster digital simulators. In this paper, we investigate a multi-transputer-based method for speeding up gate-level digital timing simulation, the acknowledged 'workhorse' of the digital circuit design verification process. In particular, we describe a variant of the basic conservative method for distributed discrete-event simulation and we present PARSIM, a gate-level digital timing simulator which is based on this method and which runs on arrays of transputers. Preliminary results on small transputer arrays demonstrate good speed-ups for bitslice partitions of circuits with regular structure, including supralinear speed-ups for a large (1664-gate) circuit. Although these results are encouraging, poor results for less-than-ideal partitions of our test circuits suggest that we require an improvement in the efficiency of deadlock resolution and/or a means of automated optimized partitioning before PARSIM can be used as a practical tool for speeding up gate-level simulation.