Verification of power losses in the gate circuit in selected MOSFET transistors based on Si and SiC

被引：1
|
作者：
Przybyla, Krzysztof [1 ]
机构：
[1] Politech Slaska, Katedra Energoelekt Napedu Elektrycznego & Roboty, Ul Boleslawa Krzywoustego 2, PL-44100 Gliwice, Poland
来源：
PRZEGLAD ELEKTROTECHNICZNY | 2018年 / 94卷 / 01期
关键词：
power losses; MOSFET; gate circuit; SiC;
D O I：
10.15199/48.2018.01.33
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Measurement results of power losses in the gate circuit in Si: APT5010JFLL, IXFN44N80P and SiC: APT40SM120J MOSFET transistors are presented in the paper. Measurements were taken in class DE inverter configuration in frequency range from 275 kHz to 525 kHz and with inverter supply voltage E=0 V and E=300 V. The article contains also the comparison of evaluated power loss values, based on datasheets, with laboratory results.
引用
收藏
页码：129 / 132
页数：4
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