Implementation of high-speed fixed-point dividers on FPGA

被引：0

作者：

Sorokin, Nikolay ^{[1
]}

机构：

[1] Pacif Natl Univ, Tikhookeanskaya str,136, Khabarovsk 680035, Russia

来源：

JOURNAL OF COMPUTER SCIENCE & TECHNOLOGY | 2006年 / 6卷 / 01期

关键词：

high-precision computations; fixed-point division; modular design; programmable logic; FPGA;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

Study deals with implementations of fixed-point division modules based on different algorithms on basis of Xilinx FPGAs. We show that our implementation of the non-restoring algorithm is significantly faster and smaller than the 32-bit IP Core "Pipelined Divider" from Xilinx. For example, the speed of the 32-bit designed module is almost 245 MHz vs. 193 MHz from Xilinx divider. Moreover, high-speed parameterized modules are designed to provide arbitrary precision of the fixed-point division, for example, with 64-bit or 128-bit operands and large fixed-point result.

引用

页码：8 / 11

页数：4

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