A BIPOLAR-BASED 0.5 MU-M BICMOS TECHNOLOGY ON BONDED SOI FOR HIGH-SPEED LSIS

被引：0
|
作者：
YOSHIDA, M
HIRAMOTO, T
FUJIWARA, T
HASHIMOTO, T
MURAYA, T
MURATA, S
WATANABE, K
TAMBA, N
IKEDA, T
机构：
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1994年 / E77C卷 / 08期
关键词：
BICMOS; BONDED SOI; DOUBLE POLYSILICON BIPOLAR; TRENCH ISOLATION; STRESS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new BiCMOS process based on a high-speed bipolar process with 0.5 mum emitter width has been developed using a bonded SOI substrate. Double polysilicon bipolar transistors with the trench isolation, shallow junctions and the pedestal collector implantation provide a high cut-off frequency of 27 GHz. Stress induced device degradation is carefully examined and a low stress trench isolation process is proposed.
引用
收藏
页码：1395 / 1403
页数：9
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