CHARACTERIZATION OF CHARGE TRAPPING IN SUBMICROMETER NMOSFETS BY GATE CAPACITANCE MEASUREMENTS

被引：17

作者：

LING, CH ^{[1
]}

YEOW, YT ^{[1
]}

AH, LK ^{[1
]}

机构：

[1] UNIV QUEENSLAND,DEPT ELECT ENGN,ST LUCIA,QLD 4072,AUSTRALIA

来源：

IEEE ELECTRON DEVICE LETTERS | 1992年 / 13卷 / 11期

关键词：

D O I：

10.1109/55.192848

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Trapping of net positive charge at low gate stress voltage, and of net negative charge at high gate stress voltage, is observed through changes in the gate-to-drain capacitance of the stressed junction. These observations can be explained in terms of electron trapping, hole trapping, and generation of acceptor-like interface states located in the upper half of the bandgap. Channel shortening is also observed and found to exhibit a logarithmic time dependence.

引用

页码：587 / 589

页数：3

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