AN INTEGRATED 16-CHANNEL CMOS TIME TO DIGITAL CONVERTER

被引：42

作者：

LJUSLIN, C

CHRISTIANSEN, J

MARCHIORO, A

KLINGSHEIM, O

机构：

[1] CERN, CERN, Geneva

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1994年 / 41卷 / 04期

关键词：

D O I：

10.1109/23.322866

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An integrated 16-channel Time to Digital Converter (TDC) for use in the NA48 [1] experiment at CERN has been developed in a 1mum CMOS technology. The resolution is 1.56ns and the total time history is 204.8ms. Buffering of up to 128 hits is done in on-chip FIFOs. The chip area is 25 mm2. The vernier circuit consists of a 16-tap voltage-controlled delay chain controlled by a Delay Locked Loop (DLL). Read out is possible at 40 MHz. JTAG/IEEE 1149.1 protocol has been incorporated to allow in-site testing of the chip. The JTAG data path is also used to access internal control and status registers.

引用

页码：1104 / 1108

页数：5

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