A 0(1)-ALGORITHM FO RMODULO ADDITION

被引：5

作者：

ELLEITHY, KM

BAYOUMI, MA

机构：

[1] The Center for Advanced Computer Studies, University of Southwestern Louisiana, Lafayette

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS | 1990年 / 37卷 / 05期

基金：

美国国家科学基金会;

关键词：

Computer Systems Programming - Computers; Digital--Adders - Integrated Circuits; VLSI - Numbering Systems;

D O I：

10.1109/31.55001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A θ(1) algorithm for large modulo addition for residue number system (RNS) based archictectures is proposed. The addition is done in a fixed number of stages which does not depend on the size of the modulus. The proposed modulo adder is much faster than the previous adders and more area efficient. The implementation of the adder is modular and is based on simple cells which leads to efficient VLSI realization. © 1990 IEEE

引用

页码：628 / 631

页数：4

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