A SURVEY OF CACHE COHERENCE SCHEMES FOR MULTIPROCESSORS

被引：95

作者：

STENSTROM, P

机构：

来源：

COMPUTER | 1990年 / 23卷 / 06期

关键词：

D O I：

10.1109/2.55497

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

[No abstract available]

引用

页码：12 / 24

页数：13

共 14 条

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ARCHIBALD, J ;

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ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1986, 4 (04) :273-298

[3]

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[4]

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[5]

Goodman J. R., 1988, 15th Annual International Symposium on Computer Architecture. Conference Proceedings (Cat. No.88CH2545-2), P422, DOI 10.1109/ISCA.1988.5253

[6]

HARIDI S, 1989, P PARLE 89, V1, P1

[7]

Karlin A. R., 1986, 27th Annual Symposium on Foundations of Computer Science (Cat. No.86CH2354-9), P244, DOI 10.1109/SFCS.1986.14

[8]

MIN SL, 1989, 1989 P INT C PAR PRO, P23

[9]

Rudolph L., 1984, 11th Annual International Symposium on Computer Architecture. Conference Proceedings (Cat. No. 84CH2051-1), P340, DOI 10.1145/800015.808203

[10] LINE (BLOCK) SIZE CHOICE FOR CPU CACHE MEMORIES [J].

SMITH, AJ .

IEEE TRANSACTIONS ON COMPUTERS, 1987, 36 (09) :1063-1075

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