ON AN IMPROVED DESIGN APPROACH FOR C-TESTABLE ORTHOGONAL ITERATIVE ARRAYS

被引：14
作者：
HUANG, WK [1 ]
LOMBARDI, F [1 ]
机构：
[1] UNIV COLORADO,DEPT ELECT & COMP ENGN,BOULDER,CO 80309
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1988年 / 7卷 / 05期
关键词：
D O I：
10.1109/43.3199
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
LOGIC DESIGN
引用
收藏
页码：609 / 615
页数：7
相关论文
共 12 条
[1]  
Breuer M. A., 1976, DIAGNOSIS RELIABLE D
[2]  
CHENG WT, 1986, P FTCS, V16, P76
[3]   C-TESTABILITY OF TWO-DIMENSIONAL ITERATIVE ARRAYS [J].
ELHUNI, H ;
VERGIS, A ;
KINNEY, L .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1986, 5 (04) :573-581
[4]   EASILY TESTABLE ITERATIVE SYSTEMS [J].
FRIEDMAN, AD .
IEEE TRANSACTIONS ON COMPUTERS, 1973, C 22 (12) :1061-1064
[5]  
HENNIE FC, 1961, ITERATIVE ARRAYS LOG
[6]  
HUANG WK, C TESTABILITY 2 DIME
[7]  
KUNG HT, 1982, COMPUTER, V15, P37, DOI 10.1109/MC.1982.1653825
[8]  
KWANG K, 1984, COMPUTER ARCHITURE P
[9]  
LEIGHTON FT, 1985, IEEE T COMPUT, V34, P448
[10]  
Mead C., 1980, INTRO VLSI SYSTEMS
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