Open-Source JTAG Simulator Bundle for Labs

被引:0
作者
Shibin, Konstantin [1 ]
Devadze, Sergei [1 ]
Rosin, Vjatseslav [1 ]
Jutman, Artur [2 ]
Ubar, Raimund [2 ]
机构
[1] Testonica Lab Raja 15, EE-12618 Tallinn, Estonia
[2] Tallinn Univ Technol, Dept Comp Engn, Tallinn, Estonia
关键词
JTAG; boundary scan; IEEE; 1149.1; Trainer; 1149; goJTAG;
D O I
10.2478/v10177-012-0032-4
中图分类号
TN [电子技术、通信技术];
学科分类号
0809 ;
摘要
This paper presents a software/ hardware bundle for studying, training and research related to IEEE 1149.1 Boundary Scan (BS) standard. The presented package includes a software environment Trainer 1149 that is capable to graphically visualize BS facilities and perform fine-grain simulation of BS test process. Trainer 1149 provides a cozy graphical design and simulation environment of BS-enabled chips and non-BS clusters. It provides the user with a full flexibility in working with any type of BS structures by supporting standard formats such as Boundary Scan Description Language and SVF (for defining test patterns). A special fault simulation mode allows injecting various types of interconnection faults to simulate their impact and inspect them using interactive tools. Trainer 1149 is the main component of a recent goJTAG initiative that aims at bringing JTAG tools closer to the user for both learning and experimental work purposes. The software part is implemented in multi-platform Java environment and distributed as an open-source freeware. Using a convenient low-cost USB-JTAG controller, one can also test real defects in real hardware. Such combination of features is unique for a public domain BS package.
引用
收藏
页码:233 / 239
页数:7
相关论文
共 11 条
[1]  
[Anonymous], 2011, JTAG BOUNDARY SCAN C
[2]  
[Anonymous], 2011, FT2232H DUAL HIGH SP
[3]  
[Anonymous], 2011, JTAG SCAN EDUCATOR T
[4]  
[Anonymous], 2013, 114912013 IEEE, P1
[5]  
[Anonymous], 2011, TRAINER 1149 TESTONI
[6]  
[Anonymous], 2011, TURBO TESTER
[7]  
Crosier D., 2007, TREDNS V U SHAPING E, P97
[8]  
Jutman A., 2005, IEEE EUR BOARS TEST
[9]  
Jutman Artur, 2004, P 6 INT WORKSH BOOL, P271
[10]  
The International Technology Roadmap for Semiconductors, 2010, 2010 UPD TEST TEST E