SELF-TESTING APPROACHES FOR VLSI ARRAYS

A self-testing method which is applicable to 1- and 2-dimensional arrays, is presented. The method is based on a state-table-verification approach and a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifier for PI testability does not always detect all faults and a new response verifier for GI-testable arrays is proposed. CGI-testable arrays which are simultaneously C and GI testable, are analysed. It is proved that a C-testable 1-dimensional array with n cells is GI testable if n greater-than-or-equal-to 2T, where T is the least common multiple of the test sequences for verifying a cell in the array. Design for testability approaches for unilateral and bilateral arrays are proposed, and similar conditions are developed for 2-dimensional arrays. Methods for reducing the size of CGI-testable unilateral and bilateral arrays are duscussed.