STATIC AND DYNAMIC NOISE MARGINS OF LOGIC-CIRCUITS

The noise margins of logic circuits are often the subject of confusion. This paper intends to clear up the confusion by explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins. Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method. In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given. Also, energy noise margins are considered. It is shown that no characteristic energy can be determined which can disturb a logic circuit. Although energy minima can be found, their values as figures of merit are doubtful. The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example. The obtained dynamic noise margins and energy noise margins of ISL agree very well with the first-order explanations given in this article. Copyright © 1979 by The Institute Of Electrical And Electronics Engineers, Inc.