共 12 条
- [1] Linear timing analysis of SOC synchronous circuits with level-sensitive latches 15TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2002, : 358 - 362
- [4] The retiming of single-phase clocked circuits containing level-sensitive latches TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1999, : 402 - 407
- [6] Advanced timing of level-sensitive sequential circuits ICECS 2004: 11th IEEE International Conference on Electronics, Circuits and Systems, 2004, : 603 - 606
- [7] Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops ASP-DAC 2006: 11TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 2006, : 941 - 946
- [10] A 0.8-1.2GHz single-phase resonant-clocked FIR filter with level-sensitive latches PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 583 - 586