HIGH-SPEED PARALLEL VLSI ARCHITECTURES FOR IMAGE DECORRELATION

被引：0

作者：

ACHARYA, T

MUKHERJEE, A

机构：

[1] UNIV MARYLAND,INST ADV COMP STUDIES,COLLEGE PK,MD 20742

[2] UNIV CENT FLORIDA,DEPT COMP SCI,ORLANDO,FL 32816

来源：

INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE | 1995年 / 9卷 / 02期

关键词：

CODEC; COMPRESSION; DECOMPRESSION; DECORRELATION; JPEG; PARALLEL ARCHITECTURE; PREDICTIVE CODING; VLSI;

D O I：

10.1142/S021800149500016X

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

We present a new high speed parallel architecture and its VLSI implementation to design a special purpose hardware for real-time lossless image compression/decompression using a decorrelation scheme. The proposed architecture can easily be implemented using state-of-the-art VLSI technology. The hardware yields a high compression rate. A prototype 1-micron VLSI chip based on this architectural idea has been designed. The scheme is favourably comparable to the lossless JPEG standard image compression schemes. We also discuss the parallelization issues of the lossless JPEG standard still compression schemes and their difficulties.

引用

页码：343 / 365

页数：23

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