STUDIES IN VLSI TECHNOLOGY ECONOMICS .4. MODELS FOR GATE ARRAY DESIGN PRODUCTIVITY

被引：1

作者：

FEY, CF ^{[1
]}

PARASKEVOPOULOS, DE ^{[1
]}

机构：

[1] NATL SEMICOND CORP,SANTA CLARA,CA 95051

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1989年 / 24卷 / 04期

关键词：

Logic Devices--Gates - Microelectronics--Economics;

D O I：

10.1109/4.34096

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An empirical model of design productivity is presented and its implications for current and future design are discussed. Model and observed values correlate well (the correlation coefficient is 0.85). The analysis encompasses 70 designs, primarily gate arrays, of up to 25,000 gates from five major corporations, designed during 1983-1988. The estimate of design productivity enables the determination of normalized productivity, manpower, and schedule. The normalized design productivity adjusts for differences in the design tasks, permitting standardized productivity measurements for planning and for benchmarking.

引用

页码：1085 / 1091

页数：7

共 22 条

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