VLSI ARCHITECTURES FOR MULTIDIMENSIONAL TRANSFORMS

被引：6

作者：

CHAKRABARTI, C ^{[1
]}

JAJA, J ^{[1
]}

机构：

[1] UNIV MARYLAND,INST ADV COMP STUDIES,DEPT ELECT ENGN,SYST RES CTR,COLLEGE PK,MD 20742

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1991年 / 40卷 / 09期

关键词：

AREA-TIME TRADEOFFS; AT2; OPTIMAL; MULTIDIMENSIONAL TRANSFORMS; ROTATOR UNIT; SUBBLOCK ROTATOR UNIT; SUBBLOCK TRANSPOSE UNIT; VLSI ARCHITECTURE;

D O I：

10.1109/12.83648

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we propose a family of VLSI architectures with area-time tradeoffs for computing (N x N x ... x N) d-dimensional linear separable transforms. For fixed-precision arithmetic with b bits, the architectures have an area A = O(N(d) + 2a), computation time T = O(d N(d/2-a)b) and achieve the AT2 bound of AT2 = O(n2b2) for constant d, where n = N(d) and 0 < a less-than-or-equal-to d/2.

引用

页码：1053 / 1057

页数：5

共 9 条

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[2]

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[3]

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[4]

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[5]

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[7]

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[8]

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[9]

[No title captured]

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