METHOD FOR REALIZATION OF FAIL-SAFE ASYNCHRONOUS SEQUENTIAL CIRCUITS

被引：9

作者：

MUKAI, Y ^{[1
]}

TOHMA, Y ^{[1
]}

机构：

[1] TOKYO INST TECHNOL, DEPT ELECTR, TOKYO, JAPAN

来源：

关键词：

D O I：

10.1109/T-C.1974.224022

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：736 / 739

页数：4

共 5 条

[1] PATTERSON WW, 1972, JUN INT S FAULT TOL
[2] SAWIN DH, 1972, JUN INT S FAULT TOL
[3] TAN CJ, 1971, IEEE T COMPUT, VC 20, P382, DOI 10.1109/T-C.1971.223253
[4] REALIZATION OF FAIL-SAFE SEQUENTIAL MACHINES BY USING A K-OUT-OF-N CODE
TOHMA, Y
OHYAMA, Y
SAKAI, R
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1971, C 20 (11) : 1270 - &
[5] INTERNAL STATE ASSIGNMENTS FOR ASYNCHRONOUS SEQUENTIAL MACHINES
TRACEY, JH
[J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1966, EC15 (04): : 551 - +