Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip

被引:8
|
作者
Shafik, Rishad Ahmed [1 ]
Al-Hashimi, Bashir M. [2 ,3 ]
Kundu, Sandip [4 ]
Ejlali, Alireza [5 ,6 ]
机构
[1] Univ Southampton, Sch Elect & Comp Sci, Southampton SO17 3AS, Hants, England
[2] Univ Southampton, Sch Elect & Comp Sci, Comp Engn, Southampton SO17 3AS, Hants, England
[3] Univ Southampton, Sch Elect & Comp Sci, Pervas Syst Ctr, Southampton SO17 3AS, Hants, England
[4] Univ Massachusetts, Dept Elect & Comp Engn, Elect & Comp Engn, Amherst, MA 01003 USA
[5] Sharif Univ Technol, Dept Comp Engn, Comp Engn, Tehran 113658639, Iran
[6] Univ Southampton, Elect Syst Design Grp, Southampton, Hants, England
基金
英国工程与自然科学研究理事会;
关键词
Multiprocessor System-on-Chip; Power Management; Voltage/ Frequency Scaling; Reliable Design; Soft Error Rate;
D O I
10.1166/jolpe.2009.1016
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
There is growing interest in evaluating the impact of soft errors on multiprocessor system-on-chip (MPSoC) at application-level rather than architectural-level, particularly in multimedia applications to optimize system design. This has recently led to the concept of application-level correctness. In this paper, we consider the relationship between application-level correctness and system-level power management using voltage scaling technique with the aim to generate designs that are optimized in terms of power consumption, while providing acceptable application-level correctness and meeting real-time performance deadlines. We propose a novel voltage scaling technique based on linear programming capable of identifying the appropriate supply voltage and frequency values of the processing cores in an MPSoC such that the power consumption is minimized for a given soft error rate (SER) and a specified performance deadline. We evaluate the effectiveness of our technique using an MPEG-2 video decoder as a case study and with peak signal-to-noise ratio (PSNR) as the application-level correctness metric. We show that the proposed voltage scaling technique can achieve up to 85% power reduction for SER of 3 - 98x10-8, while maintaining acceptable levels of real-time performance (29 frames/ s) and application-level correctness (30 dB PSNR). The above case study is based on an MPSoC architecture with four processing cores. We have also investigated the effect of varying the number of processing cores (architecture allocation) and application task mapping (distribution of tasks among cores of the MPSoC architecture) on the trade-offs between application-level correctness and power consumption minimization using the proposed voltage scaling technique.
引用
收藏
页码:145 / 156
页数:12
相关论文
共 25 条