A CONSTRUCTION METHOD OF HIGH-SPEED DECODERS USING ROMS FOR BOSE-CHAUDHURI-HOCQUENGHEM AND REED-SOLOMON CODES

被引：0
|
作者：
OKANO, H [1 ]
IMAI, H [1 ]
机构：
[1] YOKOHAMA NATL UNIV,DEPT ELECT & COMP ENGN,YOKOHAMA,KANAGAWA 240,JAPAN
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1987年 / 36卷 / 10期
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：1165 / 1171
页数：7
相关论文
共 50 条
  • [21] Design of High-Speed Errors-and-Erasures Reed-Solomon Decoders for Multi-Mode Applications
    Lu, Yung-Kuei
    Shieh, Ming-Der
    Kuo, Wen-Hsuen
    2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 199 - 202
  • [22] A high-speed pipelined degree-computationless modified euclidean algorithm architecture for Reed-Solomon decoders
    Lee, Seungbeoin
    Lee, Hanho
    Shin, Jongyoon
    Ko, Je-Soo
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 901 - +
  • [23] A flexible architecture for block turbo decoders using BCH or Reed-Solomon components codes
    Piriou, Erwan
    Jego, Christophe
    Adde, Patrick
    Jezequel, Michel
    IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2006, : 430 - +
  • [24] Construction of deletion correcting codes using generalized Reed-Solomon codes and their subcodes
    Tonien, Dongvu
    Safavi-Naini, Reihaneh
    DESIGNS CODES AND CRYPTOGRAPHY, 2007, 42 (02) : 227 - 237
  • [25] SIMPLE PROGRAMMABLE PROCESSOR FOR DECODING REED-SOLOMON CODES IN COMPACT DISK DEVICES AT HIGH-SPEED
    KO, CC
    TJHUNG, TT
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1989, 67 (01) : 15 - 25
  • [26] High-speed VLSI architecture for parallel Reed-Solomon decoder
    Lee, H
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 320 - 323
  • [27] A low-complexity, high-speed Reed-Solomon decoder
    Lee, H
    Azam, A
    IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2003, : 127 - 130
  • [28] High-speed VLSI architecture for parallel Reed-Solomon decoder
    Lee, H
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2003, 11 (02) : 288 - 294
  • [29] Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs
    Flocke, A.
    Blume, H.
    Noll, T. G.
    ADVANCES IN RADIO SCIENCE, 2005, 3 : 271 - 276
  • [30] HIGH-SPEED REED-SOLOMON DECODER FOR CORRECTING ERRORS AND ERASURES
    WEI, CH
    CHEN, CC
    LIU, GS
    IEE PROCEEDINGS-I COMMUNICATIONS SPEECH AND VISION, 1993, 140 (04): : 246 - 254
12345