AN ARCHITECTURE FOR ADDITION AND SUBTRACTION OF LONG WORD-LENGTH NUMBERS IN THE LOGARITHMIC NUMBER SYSTEM

This paper describes an architecture for performing addition and subtraction of numbers in the logarithmic number system using small lookup tables. Previous implementations require approximately 4 × 2F words for F bits of precision in the fraction. This paper shows how to reduce the size of the lookup table to fewer than [Formula omited] words. The key to this is the use of a linear approximation of the nonlinear functions stored in the lookup tables. The functions involved are highly nonlinear in some regions, so variable size regions are used for the approximation. The replacement of the F exponential dependence on the number of words by [Formula omited] allows roughly 50% more bits of fractional precision to be obtained for a given amount of ROM. The architecture is mathematically analyzed, yielding explicit expressions for all design parameters. The approach is illustrated with an example logarithmic addition and subtraction unit using 32-bit words with 30 bit exponents containing 22 fractional bits. A factor of 118 reduction in table size compared to previous techniques is achieved for this example. © 1990 IEEE