ESP - PLACEMENT BY SIMULATED EVOLUTION

[1] Aho A. V., 1974, DESIGN ANAL COMPUTER, V1st

[2] BLANKS JP, 1985, 21ST P DES AUT C, P602

[3] BREUER MA, 1977, J DES AUTOM FAULT, V1, P343

[4] CASOTTO A, 1987, IEEE T COMPUTER SEP, P838

[5] GENERATION OF MINIMAL TREES WITH A STEINER TOPOLOGY [J]. JOURNAL OF THE ACM, 1972, 19 (04) : 699 - &

[6] GENETIC PLACEMENT [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (06) : 956 - 964

[7] Donath W.E., 1980, 17TH P DES AUT C, P412

[8] DUNHAM B, 1963, SYNTHESE, P254

[9] A PROCEDURE FOR PLACEMENT OF STANDARD-CELL VLSI CIRCUITS [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (01) : 92 - 98

[10] GROVER LK, 1986, NOV P INT C COMP AID, P378

[1] Aho A. V., 1974, DESIGN ANAL COMPUTER, V1st

[2] BLANKS JP, 1985, 21ST P DES AUT C, P602

[3] BREUER MA, 1977, J DES AUTOM FAULT, V1, P343

[4] CASOTTO A, 1987, IEEE T COMPUTER SEP, P838

[5] GENERATION OF MINIMAL TREES WITH A STEINER TOPOLOGY [J]. JOURNAL OF THE ACM, 1972, 19 (04) : 699 - &

[6] GENETIC PLACEMENT [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1987, 6 (06) : 956 - 964

[7] Donath W.E., 1980, 17TH P DES AUT C, P412

[8] DUNHAM B, 1963, SYNTHESE, P254

[9] A PROCEDURE FOR PLACEMENT OF STANDARD-CELL VLSI CIRCUITS [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (01) : 92 - 98

[10] GROVER LK, 1986, NOV P INT C COMP AID, P378