14-nm FinFET 1.5 Mb Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Differential Current Sensing

被引:5
作者
Hunt-Schroeder, Eric [1 ]
Anand, Darren [1 ]
Fifield, John [1 ]
Roberge, Michael [1 ]
Pontius, Dale [1 ]
Jacunski, Mark [1 ]
Batson, Kevin [1 ]
Deming, Matthew [1 ]
Khan, Faraz [2 ]
Moy, Dan [3 ]
Cestero, Alberto [3 ]
Katz, Robert [3 ]
Chbili, Zakariae [4 ]
Banghart, Edmund [4 ]
Jiang, Liu [4 ]
Jayaraman, Balaji [5 ]
Tummuru, Rajesh R. [5 ]
Raghavan, Ramesh [5 ]
Mishra, Amit [5 ]
Robson, Norman [3 ]
Kirihata, Toshiaki [3 ]
机构
[1] GLOBALFOUNDRIES, ASIC Prod Dev Team, Burlington, VT 05452 USA
[2] Univ Calif Los Angeles, Elect & Comp Engn Dept, Los Angeles, CA 90095 USA
[3] GLOBALFOUNDRIES, Res & Technol Dev, Hopewell Jct, NY 12533 USA
[4] GLOBALFOUNDRIES, Qual & Reliabil, Malta, NY 12020 USA
[5] GLOBALFOUNDRIES, Technol Dev, Bengaluru 560045, India
来源
IEEE SOLID-STATE CIRCUITS LETTERS | 2018年 / 1卷 / 12期
关键词
Charge trap transistor (CTT); current sensing; non-volatile memory (NVM); one time programmable memory (OTPM); self-heating; twin cell;
D O I
10.1109/LSSC.2019.2899519
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An 8Kx192b charge trap transistor one time programmable memory (OTPM) is designed and manufactured in GLOBALFOUNDRIES 14-nm bulk FinFET technology without process adders or additional masks. A write timer state machine issues multicycle 192b parallel programming with per bit overwrite protection to minimize stress conditions during a write. On-chip generated voltages are temperature dependent, enabling writes and reads at military grade temperatures. A differential current sense amplifier with self-biased margining circuitry enables programming the OTPM twin cell with known repeatable margin across process-voltage-temperature. Hardware qualification certifies the OTPM to a 10-year 105 degrees C data retention specification and <3 PPM end of life bit error rate pre-ECC.
引用
收藏
页码:233 / 236
页数:4
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